As illustrated in FIG. 8, a conventional matrix-type display device incorporates a plurality of pixel electrodes 21 (represented as PIX in the figure) arranged in matrix, and a row electrode driving circuit 22 and a column electrode driving circuit 23 for turning on/off the pixel electrodes 21. Each pixel electrode 21 is connected to a switching element 24, and opening/closing of each switching element 24 is controlled by the column electrode driving circuit 23. Display data outputted from the row electrode driving circuit 22 are supplied through the switching elements 24 to the pixel electrodes 21.
As illustrated in FIGS. 9(a) and 9(b), during one horizontal scanning period, the row electrode driving circuit 22 samples and holds a video signal S.sub.in inputted during one horizontal period, in synchronization with a sampling clock signal CK.sub.s during a horizontal scanning period. Then, during the next horizontal scanning period, the data thus held are supplied as display data S.sub.Out (S.sub.out1, S.sub.out2, . . . ) to the row electrodes in a single step. The column electrode driving circuit 23 sequentially outputs scanning signals G.sub.1, G.sub.2, . . . , one signal per one horizontal scanning period, which cause the column electrodes to be turned on so that the display data S.sub.out thus supplied to the row electrodes are supplied to the pixel electrodes 21.
Thus, when the display data are supplied to the pixel electrodes 21, a display medium (liquid crystal, etc., not shown in the figures) are turned active/non-active by the pixel electrodes 21, thereby causing an image in accordance with the video signal to be displayed on a screen.
An image is displayed in a manner such that a vertical scanning is carried out with respect to each field so that the image is displayed from an upper part of the screen downward. After the scanning is completed to a lower edge of the screen, the scanning is suspended for a predetermined period of time (flyback time), and thereafter the scanning is resumed from the upper part of the screen. By repeating this process, images appear by turns on the screen.
Incidentally, TVs each having a screen at an aspect ratio of 16:9 are recently in common use, whereas TV stations have started broadcasting in a display mode for a high definition television (HDTV) and in a display mode for an extended definition television 2 (EDTV2). Therefore, among flat plate-type display devices such as liquid crystal display devices, those having laterally long screens (wide screens) come to be viewed with interest.
However, in the case where an image of the present broadcasting corresponding to the present display mode at the aspect ratio of 4:3 is displayed on the wide screen in a full display mode whereby no processing is applied, there arises a problem that display quality remarkably deteriorates. For example, an image of concentric circles appears extremely laterally long, as illustrated in FIG. 10. In the full display mode, the video signals are sampled in synchronization with rising and falling edges of a sampling clock signal CK.sub.s having a predetermined frequency, as illustrated in FIG. 13.
Therefore, in the case of a conventional CRT TV having a wide screen, an electron beam is controlled by the use of deflecting coils, so that the display quality does not deteriorate even when images in the mode for the present broadcasting are displayed. Among types of display by this method, there are a so-called normal display mode and a so-called wide display mode.
For example, in the normal display mode, an image at the aspect ratio of 4:3 is displayed only in the central part of the screen, as illustrated in FIG. 11. Therefore, the image of the concentric circles is displayed with the roundness close to 1. As a concrete method for display in the normal display mode, the Japanese Publication for Laid-open Patent Application No. 3-131182/1991 (Tokukaihei 3-131182) discloses a display method whereby an image is displayed during one effective display period (a period while an image is presented), while during a horizontal flyback period an image of a prescribed gradation level is displayed for the spaces. By this method whereby the space images are displayed during the horizontal flyback periods, a sampling frequency for sampling images is set constant.
However, since a horizontal scanning cycle, the effective display period, and the horizontal flyback period are 63.5556 .mu.s, 52.7556 .mu.s, and 10.8 .mu.s, respectively, in the case of the 4:3 display mode according to the National Television System Committee (NTSC) Broadcast Standard, the image is displayed laterally longer by 10.7 percent, which is found by the following calculation: EQU ((3/4)*(16/9)*(52.7556/63.5556)-1)*100=10.7
Note that in this case display is carried out on a screen at an aspect ratio of 16:9 in accordance with display signals supplied during one horizontal scanning period.
Therefore, in view of improving the roundness as an indicator of the display quality, it is preferable to change the sampling frequency within one horizontal period as described later. To be more specific, each sampling interval during the effective display period (effective scanning period) is preferably set 1.6283 times that during the horizontal flyback period, according to the following calculation: EQU (52.7556/10.8)/((9/3)*4/(16-(9/3)*4))=1.6283
By doing so, the roundness becomes 1.
Note that since a display screen size (aspect ratio) is determined from the viewpoint of production efficiency, the aspect ratio subtly varies with widths across corners of individual display screens. This is because glass substrates for the screens actually cut out from a mother glass have aspect ratios of 16:9.1, 15.9:9, etc. in the case of wide screens, so that as many glass substrates as possible can be obtained. Therefore, the use of the same sampling frequency may cause the roundness to deteriorate. Therefore, anyway, the clock frequency should be adjusted or changed.
In the wide display mode, as illustrated in FIG. 12, pictures are displayed in the same range of the screen as that in the full display mode, but the concentric circles displayed are closer to complete rounds in the center of the screen while have inferior roundness in the peripheral parts of the screen, compared with the concentric circles in the full display mode. Since attention is directed to the center of the screen due to the characteristics of human eyes, incongruity is less felt in the case of display in the wide display mode than in the case of display in the full display mode, even though the roundness deteriorates in the peripheral parts of the screen.
In the case where such display in the normal display mode or in the wide display mode is realized by the use of a matrix-type display device, it is necessary to modulate the sampling frequency within one horizontal scanning period. FIG. 13 illustrates respective examples of sampling timings in these display modes.
Note that in these examples, the sampling timings are in synchronization with rising and falling edges of a sampling clock signal.
In the normal display mode, the sampling frequency is switched so as to be lower, during the effective scanning period, than that during the horizontal flyback period. On the other hand, in the wide display mode, the sampling frequency is arranged so as to gradually change during the effective scanning period.
The following method has been proposed as a method for changing the sampling frequency as described above, so as to be applied to the matrix-type display device illustrated in FIG. 8. A sampling clock signal is obtained by dividing, by a frequency dividing circuit 26, a reference clock signal CK.sub.g generated by a reference clock oscillator 25 incorporating a crystal oscillator or a voltage control oscillator (VCO). Therefore, to change the sampling frequency, it is necessary to change either a division ratio 1/N (N is an integral number) of the dividing circuit 26, or a frequency of the reference clock signal CK.sub.g.
As a method for changing the frequency of the reference clock signal CK.sub.g, for example, a method whereby modulation of an oscillation frequency is carried out by voltage control by the VCO has been proposed, as disclosed in the Japanese Publication for Laid-open Patent Application No. 7-250256/1995 (Tokukaihei 7-250256).
As another method for changing the frequency of the reference clock signal CK.sub.g, the use of a circuit illustrated in FIG. 14 has been proposed. The circuit has a plurality of reference clock oscillators RG.sub.11, RG.sub.12, . . . which have different oscillation frequencies and output reference clock signals CK.sub.g1, CK.sub.g2, . . . , respectively. One reference clock signal is selected among those above by a switching circuit 27 and is outputted as the reference clock signal CK.sub.g. Thus, the reference clock signals CK.sub.g1, CK.sub.g2, . . . are sequentially chosen as the reference clock signal CK.sub.g by switching operations of the switching circuit 27 in response to switching control signals supplied from outside, thereby causing the reference clock signal CK.sub.g to have different oscillation frequencies. The switching control signals are generated at predetermined timings based on an external clock signal which has a higher frequency than that of a horizontal synchronization signal and those of the reference clock signals CK.sub.g1, CK.sub.g2, . . . .
However, in the case where the frequency is changed by dividing, realizable frequencies are limited in view of quantization, since N of the division ratio 1/N is an integral number. Specifically, sometimes a plurality of sampling frequencies obtained are not desirable even though a frequency of the reference clock signal CK.sub.g is divided using neighboring integral numbers, since a rate of change between them is too great. For example, in the case where the reference clock signal CK.sub.g has a frequency of 20 MHz and N is set to 4 and 5, sampling frequencies obtained are 5 MHz and 4 MHz, whose rate of change is 20 percent. In some cases, practically the rate of change should be not higher than 5 percent, but such a small rate of change cannot be obtained according to the above example.
So as to lower the rate of change, N may be adjusted. For example, in the case where the reference clock signal CK.sub.g has a frequency of 95 MHz and N is set to 19 and 20, sampling frequencies of 5 MHz and 4.75 MHz are obtained, whose rate of change is 5 percent. However, since N is set to a great number, the reference clock signal CK.sub.g has an extremely high frequency, thereby causing radiation to increase and costs of the display device to rise.
In the case of the arrangement wherein the reference clock signals CK.sub.g1, CK.sub.g2, . . . are switched from one to another, the sampling interval may become too small depending on the switching timings, thereby causing hitches in sampling operations by the row electrode driving circuit 22. Since provided as the row electrode driving circuit 22 is usually an integrated circuit composed of transistors or the like, a minimum sampling interval is determined depending on an operation frequency of the integrated circuit. Therefore, in the case where a sampling interval is set smaller than the minimum sampling interval thus determined, the reliability of the sampling operation of the integrated circuit cannot be ensured.
For example, as illustrated in FIG. 15, in the case where a reference clock signal CK.sub.g1 and a reference clock signal CK.sub.g2 having a cycle which is 1.5 times that of the reference clock signal CK.sub.g1 are switched from one to the other, the following may occur since the reference clock signals CK.sub.g1 and CK.sub.g2 differ in phases: in the case where a switching timing in accordance with an external clock signal, for switching from the reference clock signal CK.sub.g1 to the reference clock signal CK.sub.g2, falls in a period where the reference clock signal CK.sub.g1 is at a high level, a sampling interval in this case, as indicated by t.sub.2, may be smaller than the other sampling intervals.
In the case where a half cycle of the reference clock signal CK.sub.g1 is set to a sampling minimum interval t.sub.1 and hence the above sampling interval t.sub.2 is smaller than the minimum interval t.sub.1, it is uncertain whether the sampling is carried out during a period of the sampling interval t.sub.2. In the case where the sampling is not carried out, a pixel defect is caused, thereby causing the display quality to deteriorate.
On the other hand, in the case where the frequency of the reference clock signal CK.sub.g is changed in a display device having a VCO as the reference clock oscillator 25, the driving system has a complicated arrangement since a means for adjusting a control voltage is necessitated. Furthermore, there arises an inconvenience that costs of the display device rise, since a phase-locked loop (PLL) including a VCO capable of high-speed response is necessitated so that the frequency is changed during one horizontal scanning period (63.5 .mu.s in the case of a TV signal).